The present invention relates to data processing systems, and particularly to those which include units operating at different clock speeds and interfaces for implementing the transfer of data between such units.
Data processing systems frequently include a processor operating at a high clock speed (e.g. 1 MHz) and a batch of controllers or terminals at least some of which operate at a much lower clock speed (e.g. 250 KHz). To implement the transfer of data between circuits operating at different speeds, various interface buffering arrangements are usually provided, but these add to the cost and complexity of the system.
In addition, there is an increasing tendency to fabricate the circuits of the various units on separate large-scale-integration (LSI) chips using, for example, metal-oxide-semiconductor (MOS) transistors. The physical size of each chip depends to a great extent on the clock speed of its respective circuitry. Higher speeds require larger size components and therefore lower packing densities. However, lower packing densities are undesirable since they decrease yield, increase costs, and adversely affect power dissipation and operating speed.
Further, because of the substantial expense of designing and producing single-chip LSI circuits, it is desirable to design each chip for as many different applications as possible, such that the chip may be tailored for any particular application by merely making the appropriate connections to its input pins or terminals.